Silicon Reliability Characterization of Intel’s Foveros 3D Integration Technology for Logic-on-Logic Die Stacking

This work presents silicon reliability characterization of Intel’s Foveros three-dimensional (3D) logic-on-logic stacking technology implemented on the 22FFL process node. Simulations and data demonstrate mechanical strain safe zones around Through Silicon Vias (TSVs). Evaluations of TSV impact on transistor, interconnect, and defect reliability are reported with a Si technology focus. TSV and bump architectures pass thermomechanical assessments on the final optimized process flow. Foveros 3D stacking technology is shown to exhibit robust silicon reliability.