A 1.28pm2 Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM

This paper describes a novel contactless memory cell technology for a 3V-only 64Mbit EEPROM with NOR structure. A new prograderase scheme using a Fowler-Nordheim tunneling mechanism is developed, resulting in a single 3V power supply operation. Scatter in "low-level" threshold voltage in a memory array, which seriously affects a read operation margin at a reduced VCC in the NOR structure, is also improved with this scheme. Based on a 0.4 pm CMOS process, a small cell area of 1.28 pm2 is successfully realized by rhe contactless memory cell technology, demonstrating the 64Mbit integration capability. A single 3V power supply operation is one of the major concerns for higher density nonvolatile memories, especially in coming handheld-computers and consumer-electronics applications. To meet this requirement, some sophisticated technologies such as Source-Side-Injection FAMOS cell [l] and NAND EEPROM with Quick Intelligent hogram Architecture [2] have been proposed. However, in the SourceSide-Injection cell, the programming speed strongly depends on the single power supply voltage, which would lead to insufficient VCC margin for programming. The NAND EEPROM approach suffers from inherent disadvantages such as a large rewrite block size (4kBytes or 8kBytes) and a reduced read current compared to that of NOR structure. A schematic diagram of the proposed contactless memory may and the new prograderase scheme are shown in Fig.1, Fig.2 and Tablel, respectively. The memory array has NOR structure, with select transistors ST1 and ST2 for each block, as shown in Fig.1. Memory cells are arranged in parallel between each pair of local data and source lines, and ST1 and ST2 act as switches for connecting and disconnecting the target block to a global data line and a common source line. Fowler-Nordheim tunneling mechanism is used for both program and erase operations, as shown in Fig.2 and Tablel. The memory cell is programmed through the drain (local data line) by tunnel ejection of electrons, and is erased by tunnel injection from the whole channel region. Internal operating voltages applied to the selected word line, -9V for programming and +13V for erasing, are easily generated from the single 3V power supply voltage by on-chip voltage converters, due to a low current dissipation of tunneling. Rewrite size is as small as 512 Bytes (which corresponds to memory cells connected to each word line), suitable for various silicon file applications. Each local source line is disconnected from the common source line when programming, to allow program inhibit for the cells connected to the deselected word lines. Scatter in "low-level" threshold voltage of the programmed memory cells can be suppressed below 0.5V as shown in Fig.3, by using program and program-verify sequence. In page-mode programming for the selected word line, the program operation is controlled bit by bit, by setting the potential in each data line at 3V for successive program and at OV for program termination. Obtained tight distribution in the "lowlevel" threshold voltage would lead to successful read operation at 3V power supply voltage, without introducing a complicated word line boost scheme [3]. Schematic cross sections of the memory array parallel to a word line and a data line are shown in Fig.4. A floating gate consists of two layers of poly-Si films electrically combined each other. The fmt poly-Si defines a channel length, and the second poly-Si realizes a large capacitive coupling between the control gate and the floating gate. Obtained unit cell size is 0.8x1.6 pm2 based on a 0.4 pm CMOS process. Major memory cell parameters are summarized in Table2. SEM cross sections of the fabricated memory array parallel to a word line and a data line are shown in FigS. Figure 6 shows a top view of the fabricated memory array. Effective cell area per bit, including area overhead due to the contact and select transistors regions, is almost the same as the unit cell area as shown in Fig.7. This comes from a large number of word lines in a block (64 to 128) available in this technology, without suffering a significant degradation in cell read current. Figure 8 shows measured program and erase characteristics of a single cell. A short program and erase time less than lms is achieved at small internal operating voltages. Rogram/erase endurance characteristics of the single cell is also shown in Fig.9.