Simulation investigation of enabling technologies for EUV single exposure of Via patterns in 3nm logic technology

We explore various resolution enhancement techniques and investigate their patterning benefits for via patterns of the 3-nm logic node using computational lithography. Simulations are performed by the method of source mask optimization (SMO) using the TachyonTM software. Key assessed process parameters include edge placement error (EPE), overlap process window, image NILS, local CD uniformity and NILS depth of focus (nDOF). Simulation results show that the current mask technology employing the standard Ta-based metallic absorber does not offer enough patterning performance for vias of pitch 40 nm and below. SMO results indicate that high-absorption absorbers give a clear improvement in best-focus shift and pattern placement error while phase-shift masks result in a significant increase of NILS and nDOF. EPE improvement of multiple technologies are also investigated. Novel EUV masks together with advanced imaging with low pupil-filling ratio and curvilinear OPC, combined with highresolution and low-roughness resist and enhanced etch process are among the key enabling technologies to extend EUV single patterning to 3-nm logic via layers.