Variable Latency Carry Speculative Adders with Input-based Dynamic Configuration

Abstract This paper proposes a novel framework to design efficient variable-latency speculative adders based on a method that mixes serial/parallel prefix structures. In comparison to the conventional speculative parallel prefix adders, the proposed method eliminates the dependency of error signals, and the corresponding late completion error correction. In comparison to conventional variable latency speculative parallel prefix adders, the proposed method reduces energy-consumption by avoiding overlap in the processing of the sub-adders, overcoming the application of double prefix cell and duplicated gates. Moreover, with the proposed method, instead of having an error detection and correction circuit for low-probability errors, serial concatenations of sub-adders are considered for the worst-case. Experimental results show significant improvements in the Area-Delay Product (ADP) and Power-Delay Product (PDP) in comparison to the state-of-the-art variable latency speculative designs.