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i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing
2018
Loris Duch
Soumya Basu
Miguel Peon-Quiros
Giovanni Ansaloni
Laura Pozzi
David Atienza
Keywords:
Signal processing
Parallel computing
Computer science
SIMD
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