Design and implementation of bandpass delta-sigma modulators using half-delay integrators

Two bandpass delta-sigma A/D converters using half delay, integrators have been designed and implemented in a 2-/spl mu/m n-well double-poly double-metal CMOS process. The first design, a fourth-order architecture with an input modulation network, achieves a signal-to-noise ratio (SNR) of 73 dB over a 0.005/spl pi/ input bandwidth, while the second design, a sixth-order topology, yielded a measured SNR of 80 dB over a 0.004/spl pi/ input bandwidth.