MULTIPLE-CELL SQUARE-TYPE LAYOUT DESIGN FOR OUTPUT TRANSISTORS IN SUBMICRON CMOS TECHNOLOGY TO SAVE SILICON AREA

A new multiple-cell square-type layout design is proposed to realize the large-dimension output transistors for submicron low-voltage CMOS ICs. By using this layout design, the layout area of CMOS output buAers can be eAectively reduced 30-40% with respect to the traditional fin- ger-type layout. The drain-to-bulk parasitic capacitance of the output transistors is also reduced 40% by this square-type layout. Experimental results in a 0.6 mm CMOS process have shown that the maximum driving (sinking) capability per unit layout area of a CMOS output buAer realized by the proposed multiple-cell square-type layout is improved 54% (34%) more than that by the traditional finger-type layout. The human-body-model (machine-model) ESD robustness per unit layout area of the CMOS output buAer realized by the proposed multiple-cell square-type layout is increased 25.2% (17.3%) as comparing to that by the traditional finger-type layout. # 1998 Published by Elsevier Science Ltd. All rights reserved