Validation of process cost effective layout refinement utilizing design intent

Continuous shrinkage of design rule (DR) in ultra-large-scale integrated circuit (ULSI) devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension (CD) tolerance for each object and budgeting the tolerance for each process step. Furthermore, to extract adequate tolerance, design intent in terms of electrical behavior should be carefully considered. Electrical behavior is carefully verified in design stages using various electronic design automation (EDA) tools. However, once the design data is converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process stage. Thus, instead of essential tolerance assignment according to layout-related design intent, uniform and redundant tolerance is used, and so excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. In this paper, test flow utilizing design intent is developed. In the flow, electrical small-margin spots are extracted, verified with customized criteria according to the tolerance derived from design intent, and fixed in the process. The proposed flow is examined and validated for the application to 40nm node test chip.