An Efficient Usage Indian Vedic Shrewdness in Multiplication Module of ECC Co-Processor Architecture

Elliptic Curve Cryptography (ECC) becomes an apparent choice when the security, speed, key length and area constraints are exhorted. This paper implements the ECC over GF(2256) based on the Montgomery scalar multiplication in a field programmable gate array (FPGA) processor with the focus of minimizing the resource binding with random sequence supported by linear feedback shift register (LFSR). Multiplier is most used components of such co-processors and hence even a productive multiplier can save the resource in large extend. This paper employs an efficient multiplier devised from the ancient Indian “Vedic Mathematic Sutras”. The most efficient sutra called “Urdhva Tiryakbhayam” paves a speedy, vertical and crosswise, digital platform supportive and reversible logic implementable multiplier. The proposed ECC processor performs the 256 bit point multiplication with the power consumption of 691mW and utilizes 13918 LUTs for 100 MHz frequency when implemented in a Spartan 3E-XC3S1600E using Modelsim 5.7 and Xilinx 9.2i.