Design of an 8GSps, 65nm CMOS Wideband Flash Analog-to-Digital Converter

This paper describes the design of an 8Gsps flash Analog-to-Digital Converter (ADC) for wideband radio astronomy applications. The ADC contains a track-and-hold (TAH) and a 1-to-4 demultiplexer. Our circuit has been fabricated with the 65nm technology from STMicroelectronics. The post-layout simulations show a Figure of Merit (FoM) of 11.36pJ/conv.step and a power consumption of 480mW at Nyquist sampling condition. The ongoing tests will soon verify these predictions