The Development and the Integration of the 5 µm to 1 µm Half Pitches Wafer Level Cu Redistribution Layers

The original purpose of the Re-Distribution Layers(RDL) was to assist in the adaption of metal bumping and flipchip packaging technologies, by the addition of the metal anddielectric layers onto the wafer surface to re-route the legacydesigned irregular peripheral I/O layout, into a new area arraybond pads layout to facilitate a balanced metal bumps and flipchip bonding. The redistribution layer technology requiredpolymeric/organic thin film (e.g. BCB, Polyimide, PBO) asinsulator and with semi-additive metallization scheme (oftenCu pattern plating) to serve rerouting purpose. The redistribution trace technology, other continuing itsassociation with bumping and flip chip packaging and waferlevel chip scale packaging (WLCSP), now extend itsapplication into advanced packaging technologies, such as fanout wafer level packaging (FO WLP) and various TSV-less, substrate-less multiple chip integration, that to drive the costeffective miniaturization of system-in-package (SiP) application. The Cu RDL that in production, the line width/ line spacingare 10 micrometer (µm)/10 µm which make the full pitch of20 µm and half pitch of 10 µm. For the sake of the simplicity, half pitch will be used as index for benchmarking. In the areaof the multiple chip integration or SiP applications, particularity those that do not use laminate substrates, RDLplay an important role to interconnect multiple ICs with IOcounts in thousands to tens thousands, replacing the role ofmultiple build up layers of the laminate substrate, thus 10 µmhalf pitch no longer meet the need of connecting high densityIO and there is driving force to scale down RDL half pitch andincrease number of RDL layers, from single layers to two tothree layers of metal traces excluding under bumping metals(UBM) for attaching BGA balls. PWB industry is undergoingthe similar efforts to target to put substrate with 5 um linewidth into market. In this paper, development efforts in scaling down RDL halfpitch, with existing polymeric insulting film and Cu patternplating will be revealed. It is discovered that scaling from 10to 3 µm posed no significant technical difficulties with existingtools that are in production, as long as the Cu thickness areproportional shrunk to keep the width/ height aspect ratio. Below half pitch of 3 µm, it would be difficult to make suchfine pitch layer on top of other layers, since the topography ofmultiple RDL with any planarization, that is out of the depthof focus (DoF) range of 2 µm and 1 µm, and these 1 µm / 2 µmhalf pitches, would be limited to as the first RDL in themultiple RDL scheme. Cu dual damascene technology with CVD dielectric film (Sioxide, Si nitride) that were commonly used in the modern ICfabrication fab capable of the advanced node (90nm andbeyond), was also phased in and demonstrated that up to threelevels of 1um Cu RDL are feasible with this technology. Furthermore, hybrid integration of the fine line CVD RDLwith the RDL with polymeric dielectrics is also demonstrated.