Reduction of systematic defects through machine learning from design to fab

Maximizing yield in a modern semiconductor fab requires proper optimization of the design (layout), process technology, and fab process tool recipes. For the past decade the prevalence of systematic defects tied to design or design-process interactions have predominated over random defect sources. Previously Resolution Enhancement Technology (RET), Design For Manufacturability (DFM), and Design-Technology Co-optimization (DTCO) techniques were the successful response to eliminating systematic yield limiting patterns. Machine learning, with its ability to find trends and make predictions based on large volumes of data, provides a unique path towards further reduction in systematic defect levels. This talk will present methods based on the use of design and process info with machine learning and computational lithography methods to identify and eliminate yield limiting patterns in the design, improve the accuracy of mask generation with etch and resist modeling and OPC, and improve the productivity and accuracy of fab defect detection and diagnostics. This paper will present methods to improve EPE control and reduce systematic hotspots through both supervised and unsupervised machine learning. Specifically we will focus on 3 areas: - identifying and yield limiting patterns in the design phase. - improving the accuracy (EPE control) of mask generation with machine learning assisted etch and resist modeling and OPC. - improving the productivity and accuracy of fab defect detection and diagnostics with machine learning.