Process technology for the fabrication of a Chip-in-Wire style packaging

In this contribution, progress on chip-in-wire packaging will be presented. The basic principle behind this concept is that small chips are interconnected and embedded in a flexible (and possibly stretchable) material so that a resulting 1D array of interconnected dies can be formed. At the end of the process, the structures can be released so that a freestanding "wire" of interconnected chips is fabricated. Key characteristics of this particular packaging approach are: ultra thin chips, die embedding, die encapsulation, flexible (and stretchable) embodiments and wafer level processing. The process can be based both on individual active dies and on full active wafers. On one hand, working with individual dies allows integration of different IC's technologies in a single package. On the other hand, thinning and transfer of a full active wafer is a completely parallel approach where a whole wafer is populated at once and is therefore even more cost effective. In this paper, the chip-in-wire concept and its realization will be presented. More specifically, after a description of the concept itself and a presentation of the process flow, related process technology aspects will be described. Results of die embedded devices will be presented and specific processing aspects will be discussed.