Combining Topological & Physical Pattern Recognition To Enhance Memory Chip Reliability

The demand for both non-volatile (NAND) and volatile dynamic random access memory (DRAM) chips in processor and application-specific integrated circuit (ASIC) designs has grown tremendously in recent years, due largely to rapid advances in semiconductor technology coupled with the trending popularity of low-power smart devices. This work demonstrates a proven automated reliability checking and debugging flow that combines electrical topologies with their geometrical patterns to ensure precise verification of reliability design rule compliance, especially for low-power high-speed applications using NAND/DRAM.