Harmonic filter with low coupling capacitance for Medium Voltage, high dv/dt PWM converters

Emerging medium voltage (MV) Silicon Carbide (SiC) 10 kV MOSFETs have low on-state resistance and are capable of very high switching speeds. As a result, a highly efficient and compact MV power conversion system can be realized using these devices, which is desirable for many existing and emerging high power applications. However, at very high switching speeds in MV, leads to extremely high dV/dt during switching transitions. This gives rise to increased attention towards circuit parasitics as the parasitic capacitance of the filter components provides a path for the high-frequency current. Therefore, a very high dV/dt operation imposes a strict requirement on the parasitic capacitance of the filter components to meet the stringent conducted ElectroMangnetic Interference (EMI) standards. A design methodology to reduce the parasitic capacitance of the filter inductor in MV power conversion is proposed. The Analytical model of the parasitic capacitance is developed, and compared with finite element analysis along with actual value measurements through an impedance analyzer. The inductors performance is also evaluated experimentally using an XHV-9 module-based Power Electronic Building Block (PEBB).