Analysis of systematic variation and impact on circuit performance

Yield loss due to process variations can be classified as catastrophic or parametric. Parametric variations can further be random or systematic in nature. Systematic parametric variations are being projected as a major yield limiter in sub- 65nm technologies. Though several models exist to describe process-induced parametric effects in layouts, there is no existing design methodology to study the variational (across process window) impact of all these effects simultaneously. In this paper, we present a methodology for analyzing multiple process-induced systematic and statistical layout dependent effects on circuit performance. We describe physical design models used to describe four major sources of parametric variability - lithography, stress, etch and contact resistance - and their impact on device properties. We then develop a methodology to determine variability in circuit performance based on integrating the above device models with a circuit simulator like SPICE. A circuit simulation engine for 45nm SOI devices is implemented, which shows the extent of the impact of layout-dependent systematic variations on circuit parameters like delay and power. Based on the analysis, we demonstrate that all systematic effects need to be simultaneously included to match the hardware data. We believe a flow that is capable of understanding process-induced parametric variability will have major advantages in terms of improving physical design and yield in addition to reducing design to hardware miscorrelations and advantages in terms of diagnosis and silicon debug.