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Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier
Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier
2019
Yamazaki Mitsufumi
Sakamoto Junichi
Okuaki Yuta
Matsumoto Tsutomu
Keywords:
Field-programmable gate array
modular multiplier
bilinear pairing
Side channel attack
Computer science
Computer hardware
Pairing
Correction
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