SEE evaluation of ARM M0 cores in a 28 nm FDSOI technology

Abstract Microprocessors are widely used in space applications. ARM processors fabricated with FDSOI technologies are promising for future space programs. However, radiation-hardening approaches can greatly affect the resource overhead and performance. These hardening techniques need to be evaluated at system level to better understand their effectiveness, especially for modern CMOS technologies. In this paper, two ARM® Cortex® M0 cores, a reference core and a hardened core were implemented on the same die in a 28-nm FDSOI technology. The reference core was designed with components from the standard cell library, while the other one was implemented with hardened DICE flip-flops. Both of the cores shared the same on-chip TMR-protected SRAM. Heavy ion experiments showed that the error cross section of the core with DICE flip-flops was about 2 times smaller at LET of 40 MeV·cm2·mg−1. This suggests that the contribution from logic circuits in the microprocessor cores also need to be considered for better error reduction.