An approach to the design of RISC core processors for VLSI embedded systems

Abstract Pipelining greatly improves the performance of processors but also increases the complexity of hardware design. This leads to a trade-off between nonoptimal hardware area and clock frequency obtained from synthesis CAD tools and, in the other side, long hardware development times involving low level design and complex verification methods. This trade-off becomes more important when designing VLSI circuits for embedded applications (EAs), where a shorter design time is needed in order to modify previous core features without compromising hardware optimality. A fully-pipelined RISC core processor (“DLXcore”) for VLSI EAs adapted to real-time MPEG video compression together with the bottom-up design methodology used are presented in this paper. It is supported on VHDL synthesis in order to obtain high flexibility, abstraction and short development cycles, while manufacturer tools are used to optimize the use of the hardware resources.