A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

A precise on-chip voltage generator for gigascale DRAM's with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-/spl mu/m process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and V/sub BB/ bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAM's.