Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms

This paper discusses the performance analysis of memetic and genetic algorithms (GA and MA) as the optimising strategy for the design of embedded evolvable hardware. The optimisation algorithm with the fitness evaluation searches for the best configuration to evolve the hardware model. Here, an experimental setup is carried to intrinsically evolve combinational circuits to test the performance of MA and GA. The complete evaluation and evolution is built on a single Virtex 6 (XC6VLX240T-1FFG1156) ML605 Evaluation Kit FPGA. A virtual reconfigurable architecture (VRA) with the hardware fitness circuit is modelled as a second reconfigurable layer over the field programmable gate array (FPGA) to configure the target combinational logic. A FPGA soft core processor evaluates the search algorithm and the best solutions are utilised for the hardware evolution. The experimentation results showed that convergence and evolution time of MA was faster compared to GA when the search space was large. Thus, proving MA is a better option for large search space evaluations for evolvable hardware architectures.