Dark noise in a CMOS imager pixel with negative bias on transfer gate
2011
Negative bias on transfer gate in 4-transistor CMOS imager pixel is an efficient way to reduce dark current
generated at the Si-SiO2 interface. But further lowering of negative bias increases dark current noise. In this
paper, detailed cause analysis of dark current noise generated when negative bias is applied and the key
technology to reduce the dark current noise are shown. The dark output level of hot pixel follows a
Trap-Assisted-Tunneling (TAT) dark current electric field dependency. Device simulation shows that the
generation of high electric field is attributed to the large voltage difference between the high concentration
hole accumulation layer under negatively biased transfer gate and n- layer of FD edge along transfer gate. The
reduction of dark current in FD is experimentally observed when the n- dopnat concentration at FD edge is
decreased and when a gate insulator thickness is increased. The results show that the mechanism of the dark
current increase is Gate-Induced-Leak (GIL) TAT generated by high electric field at the edge of a FD along
negatively biased transfer gate. The reduction of the maximum electric filed at the FD edge by reducing FD
dopant concentration is one of the key to suppress the GIL - TAT dark current.
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