Evaluation of Mo-doped Ti salicide process for sub-0.18-μm CMOS

1998 
For scaled CMOS technology with gate length down to sub-0.25 micrometer, the conventional Ti salicide suffers from high polygate sheet resistance (R sheet ) due to difficulty in the low resistivity C54 TiSi 2 phase transition. To improve the sub 0.25 micrometer TiSi2 R sheet , pre-amorphization implant (PAI) was added to achieve low R sheet down to approximately 0.1 micrometer gate length, and PAI based TiSi 2 has been the base-line salicide process for current 0.25 micrometer CMOS technology. However, various studies on sub 0.18 micrometer devices have shown that PAI process tends to induce additional S/D dopant diffusion and results in the series resistance (R SD ) increase and drive current degradation, especially for pMOS transistors. On the other hand, Mo implant was found effective in enhancing the C54 TiSi 2 formation for narrow lines and has the potential to realize a simplified TiSi 2 process with one single thermal step. However, the Mo based Ti salicide is still relatively new to date, and a complete CMOS study is helpful in identifying the trade-offs for such a process. In this work, we present a detailed CMOS evaluation of Mo doped TiSi 2 process. Two different Mo based processes are studied: (1) Mo implant into gate before gate pattern (Mo-A case). In this case, the source/drain (S/D) diffusion regions have minimal Mo doping. (2) Mo implant into gate and S/D regions right before the S/D anneal (Mo-B case). For both Mo-A and Mo-B processes, we also studied the effect of Mo doses and the difference between the conventional 2-step rapid thermal process (RTP), low-temperature formation plus Ti strip plus high-temperature anneal, and the 1-step RTP process, namely low-T formation plus Ti stripe, where the high-T anneal is skipped. The results of the Mo processes are compared with three other reference salicide processes: conventional TiSi 2 without PAI (Conv.), TiSi 2 with Ge or As PAI and the emerging CoSi 2 technology. The following CMOS care-abouts are evaluated for the various salicide processes: (1) polysilicon and diffusion region R sheet , (2) various bridging mechanisms, (3) diode leakages: bottom junction, trench edge and gate edge leakage currents, (4) drive current and R SD , and (5) charge to breakdown (Q BD ).
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