Large area EUV via yield analysis for single damascene process: voltage contrast, CD and defect metrology (Conference Presentation)

In this work we show measurement results on EUV vias through full process integration; after litho (ADI), after etch (AEI) and after CMP polish (API) for a wide range of designs (regular arrays, logic, SRAM, and alignment and overlay mark designs) on a single damascene via scheme. Physical inspection (top view) and voltage contrast (VC) measurements are used to determine number of via failures at different stages of the process flow. While the physical inspection reveals vias missing and merging on top layer (at resist level ADI or hard mask AEI) the VC also can show failing vias AEI at the bottom of the via or in general failing vias API due to failing via fill during metallization and etch. Different metallization schemes including TaN vs TaNRu liners and Co vs Cu plating and CMP were compared using VC. Quantification of VC anomalies in the inspection images allows judgement of the metal fill on the single damascene via patterning across the different structures. The number of missing and merging vias AEI and API is used as a proxy for yield and this metric was used to drive process optimization. Given the large FoV of images collected on eP5 tool with a field of view 8µm x 8µm - 12µm x 12µm with 1nm or 2nm pixel size it is possible to determine both CD and defects in the same inspection for a substantial number of vias in a relatively short inspection time. Furthermore the VC inspection method is applied to an imec vehicle consisting of via chains at 32nm pitch to determine and localize failures along the via chain.