A 3.3 mW 12 MS/s 10b pipelined ADC in 90 nm digital CMOS

A 10b pipelined ADC has been realized in a digital 90 nm CMOS technology using techniques such as switched opamps and switched-input buffers. Measurements show that this ADC samples at 12 MS/s achieving a peak SNDR of 52.6 dB using a 1.2 V supply. It consumes 3.3 mW and occupies 0.3 mm/sup 2/ core area.