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A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation
A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation
2000
Hideki Sakakibara
Michiaki Nakayama
Mitsugu Kusunoki
K. Kurita
Yuji Yokoyama
Syuichi Miyaoka
Jyun-ichi Koike
Nobuo Tamba
Toru Kobayashi
Masaji Kume
Hideo Sawamoto
Atsumi Kawata
Hirotoshi Tanaka
Yoshifumi Takada
Masakazu Yamamoto
Masayoshi Yagyu
Youichi Tsuchiya
Hiroshi Yoshida
Nobuaki Kitamura
Kunihiko Yamaguchi
Keywords:
CAS latency
Parallel computing
Sense amplifier
Static random-access memory
Computer hardware
Universal memory
CPU cache
Memory rank
Cache
Pipeline burst cache
Computer science
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