A DoE of Thermal Management for FC on LTCC

The thermal management for FC (flip chip) on the LTCC has to be better understood, in order to meet this requirement. Therefore a DoE (design of experiment) was developed and LTCC-thickness, thermal vias, heatspreader and underfill were used as parameters. The test die has a heating resistor to simulate the power loss in the amplifier and a diode circuit. With the voltage drop over the diode, the die temperature can be calculated. The test die also contains a daisy chain which will be used later on for reliability investigations during thermal cycling and high temperature storage. For more detailed understanding of the thermal management an FE-model (finite element) was used. The FE-model was calibrated, using the results of the experimental setup. The usage of FE-modeling will shorten the design phase of a project significantly.