Extended SPICE-like model accounting for layout effects on snapback phenomenon during ESD events
1999
Abstract An extended SPICE-like model for snapback phenomenon including the impact of gate length and substrate on the holding voltage is presented. Substrate conduction is analytically solved thanks to a transmission line model. A fast extraction methodology is also described. This model is in good agreement with the measurements performed on deeply submicron CMOS technologies.
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
10
References
3
Citations
NaN
KQI