Solder Bump Electromigration and CPI Challenges in Low-k Devices

Understanding and managing both chip-to-package interaction (CPI) and solder bump electromigration (EM) is becoming an increasing challenge for flip chip plastic ball grid array (FCPBGA) packaging. Requirements for state-of-the-art device technologies include shrinking of feature dimensions with respect to the prior technology node, faster speed, higher power, increased die size and RoHS compliance. To meet these requirements, device designs typically employ promising new low-k dielectric materials, unique construction elements, copper interconnections and Pb-free solder bumps.