Automatic Synthesis of Boolean Expression and Error Detection from Logic Circuit Sketches

Automatic techniques to recognize and evaluate digital logic circuits are more efficient and require less human intervention, as compared to, traditional pen and paper methods. In this paper, we propose LEONARDO (Logic Expression fOrmatioN And eRror Detection framewOrk), a hierarchical approach to recognize boolean expression from hand drawn digital logic gate diagram. The key contributions in the proposed approach are: (i) a novel hierarchical framework to synthesize boolean expression from a hand drawn logic circuit diagram; and (ii) identification of anomalies in drawing. Extensive experimentation was performed through qualitative and quantitative analysis. Results were also compared with existing techniques proposed on the similar problem. Upon experimentation and analysis, our system proved to be more robust to user variability in design and yielded an accuracy of \(95.2\%\), which is a \(4\%\) gain over others.