cost effective ceramic surface maount packaging for high I/O applications

Ever since the push to eliminate through hole technology for maximized component density on printed wiring boards (PWB's), the cost for the surface mourd technology (SMT) packages has escalated for high lead count devices (greater than ISO leads). The primary reason for this Increase is the fact that to achieve reasonable package densities on the printed wiring boards (PWB's), fine pitch leaded devices are a necessity (less than 25 ml lead pitch). The industry is in desperate need of a cost effective SMT package design, and the Ceramic Sall Grid Array (CBGA) andVor the Ceramic Colurm Grid Array (CCGA) packages are the solution. This paper primarily focuses in on Ceramic Sall Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packaging, but does go into discussion of all existing packaging schemes on the market today for large die (greater than Srorn). Specifically, the advantages and disadvantages of fine pitch devices, detailed description of the 1.00mm interconnect pitch CBGA/CCGA packages, CBGA/CCGA standard package offerings (JEDEC registered), general package comparisons to each other (in the areas of thermal performance, electrical performance, size, cost, and overall cornponerl density on the PWB), soldier interconnect fatigue properties of the CBGA/CCGA (i.e. predicted and measured low cycle fatigue go of the device soldier interconnect inspection of the CBGA/CCGA (should Inspection be performed?), test and burn-in of the CBGA/CC devices, CBGA/CCGA device shipping method for pick and place and/or manual assembly, how to perform CBGA/CCGA board attach on existing PWB's (i.e. what are the manufacturing process differences for the CBGA/CCGA board attach process), and finally how to layout the PWB breakout pattern for the CBGA/CCGA to minimize the numbered PWB muting layers.