VLSI design of a neural processing element for the Boltzmann machine

The VLSI design of a neural processing element (NPE) of a massively parallel architecture for the Boltzmann machine algorithm is described. The single instruction, multiple data (SIMD) organization of the architecture and the algorithm itself require each NPE to have a large local memory and a simple datapath. This project combines reduced instruction set computer (RISC)-like datapath and a high capacity DRAM in the same silicon die with a digital technology, in order to reduce PCB costs by implementing each node of the architecture with a single ASIC. >