Improved dual-capacitive arrays DAC architecture for SAR ADC

An improved dual-capacitive arrays DAC (IDCA-DAC) architecture for successive approximation register ADC is presented. By using a switching-back switching scheme and a third reference voltage for the last bit conversion, the proposed IDCA-DAC architecture achieves 42% savings in average switching energy and 47.1% reduction in area compared with the original DCA-DAC architecture. Additionally, it can achieve 99.3% savings in average switching energy and 71.9% reduction in area compared with the conventional method.