Using Natural Version Redundancy of FPGA Projects in Area of Critical Applications

The paper focuses on the role of version redundancy, which increases with the expansion of critical applications and the tightening of their functional safety requirements. International standards governing these requirements have already fixed the importance of version redundancy to counter common cause failures in safety-related systems. The problem of hidden faults inherent in these systems is equally acute, undermining confidence in the fault tolerance of circuit solutions important for functional safety. We suggest that this problem be seen as a growth problem where the system rises to the level of diversification in modes of operation by dividing them into normal and emergency and checkability circuits, but components continue to be stamped at a lower level of replication. Then the solution to the problem is to raise the components to the level of the system by developing their version redundancy. We demonstrate this development for FPGA components with LUT-oriented architecture and offer a method to improve the FPGA-ready project by natural version redundancy of its program code. The method generates a set of program code versions and selects versions that improve the checkability of circuits with respect to constant faults and the trustworthiness of results, respectively, in normal and emergency mode to reduce a set of hidden faults. The method is illustrated by an iterative array multiplier implemented in an FPGA project. Versions are generated, evaluated, and selected using the program developed for this.