Minimizing Bank Conflict Delay for Real-Time Embedded Multicore Systems via Bank Mapping

Multi-core architectures may meet the increasing performance requirement of real-time systems. However, it is harder to compute the WCET estimation in multi-core platforms due to inter-task interference that tasks suffer when accessing shared hardware resources. In this paper, we propose a finer grained approach to analyze the inter-task interference for multi-core platforms with the TDMA policy and bank-column cache partitioning, and our approach can reasonably estimate inter-task interference delays. Moreover, we make bank-to-core mapping to optimize the interference delays, and develop an algorithm for finding the best bank-to-core mapping. The experimental results show that our interference analysis approach can improve the tightness of interference delays by 14.68% on average compared to Upper Bound Delay (UBD) approach, and the optimized bank-to-core mapping can achieve the WCET improvement by 9.27% on average.