14–bit, 2.2MS/s sigma delta ADCs

This paper presents the design and test results of a 4th and 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator and digital decimator sections were implemented in a .35µM CMOS, double poly, triple level metal 3.3v process. The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation.