Eliminating the offset between overlay metrology and device patterns using computational metrology target design

Designing metrology targets that mimic process device cell behavior is becoming a common component in overlay process control. For an advanced DRAM process (sub 20 nm node), the extreme illumination methods needed to pattern the critical device features makes it harder to control the aberration induced overlay delta between metrology target and device patterns. To compensate for this delta, a Non-Zero-Offset is applied to the metrology measurement that is based on a manual calibration measurement using CD-SEM Overlay. In this paper, we document how this mismatch can be minimized through the right choice of metrology targets and measurement recipe.