Design and fabrication of a tri-C30 multichip module building block

A real-time architecture was designed, developed and fabricated that targets an application through the MiP (Monolithic Interceptor Processor) program. This MCM, as an elemental building block for parallel real-time DSP applications was designed and built in the standard MiP size and format. This PDA (Parallel Digital signal processing Array) is capable of 400 MFLOPS (at 33 MHz) within a volume of 2 in/sup 3/. Due to the minimized circuit parasitics of HDI packaging, much higher clock speed, hence MFLOPS, are quite likely. Though the evaluation of the PDA was not completed, the MiP project developed what could be the smallest and most capable real-time PDA to date. In order to support intermediate testing, a key "known good module" test fixture was also developed. It then provided for the demonstration of key design and methodologies that continue to be used.