CacheLeakage: A leakage aware cache simulator

In very deep submicron technologies, limiting the growing on-chip power consumption in memories is a major challenge for SoC designers. Accurate modeling of power, early in the design stage is thus crucial for system level power estimation. In this paper, we present an enhanced cache memory simulator that models leakage reduction techniques such as the dual-V t , dual-T ox , NC-SRAM, and gated-V dd techniques which can be applied to the SRAM cell structure to reduce the overall leakage power. We also examine the power/speed trade-offs associated with each leakage reduction technique, at the system level using a cycle-accurate processor simulator. CacheLeakage thus helps in choosing the right memory configurations. Simulation results show a trade-off between power and performance and we see upto 60% reduction in leakage power, at low performance overhead.