A new auto-lock circuit concept guaranteeing low jitter in PLL frequency synthesizers irrespective of process variations

A new auto-lock circuit concept is presented for PLL synthesizers. This concept was applied to a 622 MHz embedded BiCMOS PLL. It guarantees that the PLL automatically locks at (622 MHz/spl plusmn/10%) with less than 40 ps intrinsic peak-to-peak jitter irrespective of process variations and maintains this lockover 0/spl deg/C to 125/spl deg/C operating temperature range. This auto-lock circuit requires no external pins or expensive trimming process.