Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate

This paper reports the TCAD based investigation of the DC/RF and linearity characteristics of a newly proposed dual-material (DM) laterally-stacked (LS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (LS-STFET). Device-level performance comparison is made between the proposed TFET with a dual-material (DM) vertically-stacked (VS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (VS-STFET). Low bandgap material Ge is used in the source region to form a Ge (source)/Si (channel) heterojunction for enhancing the ON-state current of the presented TFETs. The effects of both donor (+ ve) and acceptor (−ve) type interface trap charges at the channel/SiO2 region on the DC, analogue/RF and linearity figure of merits have been analyzed for both the devices under study. The LS-STFET is shown to possess higher ON-state current and smaller subthreshold swing (SS) over the VS-STFET. In addition, the LS-STFET is shown to have better DC, analog/RF and linearity performance over VS-STFET in the presence of the donor and acceptor interface trap charges.