Dynamic partial reconfiguration enchanced with security system for reduced area and low power consumption

Abstract Field-programmable gate arrays (FPGAs) have travelled far from just being utilized as glue logic to an entire system solution. This is mostly due to their generalized re-configurable nature, lower non-recurring engineering (NRE) expense, and also fast time to market. Owing to the reconfigurable nature of FPGA, a new field called reconfigurable computing that can change the circuit configuration after hardware production came into existence. Application of re-configurable computing for self-adaptive hardware allows hardware to get adapt to various environmental conditions and different needs by swapping or loading disparate computational modules. This work proposes an effectual design methodology (enhanced DPR security system (EDPRSS)) utilized to execute high performance FPGA device in respect of low power consumption along with security for the area reduction. In the proposed technique, hash code generation (HCG) and encryption hardware accelerators can well be dynamically produced on FPGA utilizing partial re-configuration as stated by the application requisites. The system is competent to swap in or swap out the equivalent hardware accelerator during run time, which in turn diminishes the power and area. Here, 2 re-configurable partitions are produced for encryption and also HCG algorithm. Experiential outcomes proved that the proposed technique proffers better performance when contrasted to the other conventional systems.