Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer

Abstract A novel SOI LDMOS with a partial compound buried layer structure (P-CBL SOI) is proposed in this paper. The buried oxide layer at the source-side is replaced by a compound buried layer (CBL) of “top oxide-middle polysilicon-bottom oxide”, and the buried oxide layer at the drain-side is just as the conventional SOI LDMOS (C-SOI). Firstly, a new peak of electric field is introduced at the interface and the whole lateral electric field in the top silicon layer is modulated, resulting in a higher lateral BV . Secondly, impurity doping meeting the RESURF effect in the top silicon layer is higher because the top oxide is thinner than the conventional buried oxide layer, leading to a lower R on , sp at the on-state and an enhanced vertical BV at the off-state. Finally, thermal conductivity of polysilicon is higher than that of SiO 2 , offering a lower self-heating effect. The influences of structure parameters on the devices performances are investigated. Compared with those of C-SOI LDMOS on the same top silicon layer of 4 μm, buried dielectric layer of 4 μm, and drift region of 40 μm, BV of P-CBL SOI LDMOS is enhanced by 33.4%, R on , sp is reduced by 37.4%, and the maximum temperature at the power of 1 mW/μm is depressed by 13.3 K, respectively.