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A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links
A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links
2019
Heejae Hwang
Jongsun Kim
Keywords:
Electronic engineering
Process variation
Computer science
Duty cycle
Input/output
duty cycle corrector
high speed memory
Dram
memory interface
Correction
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