High-Level Modeling of Network-on-Chip

This report describes the design, implementation and testing of a high-level model of an asynchronous network-on-chip called MANGO that has been developed at IMM, DTU. The requirements to the model are twofold: It should be timing accurate, which allows it to be used in place of MANGO, and it should have a high simulation speed. For these purposes, different approaches to modeling network-on-chip and asynchronous circuits have been investigated. Simulation results indicate a simulation speedup on a magnitude of a factor 1000 over the current implementation of MANGO, which is implemented as netlists of standard cells.