Layout considerations in power amplifiers with negative parallel feedback

In this paper, we discuss layout problems encountered in power amplifiers with negative parallel feedback. We show how to reduce the risk of an unstable power amplifier (PA) by careful layouting without the use of additional elements and thus chip area. Optimised vs. non-optimised layouting are compared and verified with fabricated ICs. Finally a PA with large signal bandwidth of 1.9 GHz at a design frequency of 2.6 GHz using negative feedback in a standard 250 nm BiCMOS technology is introduced. An efficiency of 34% and an output power of 26.9dBm at the 1 dB compression point were measured.