Low-Complex and Low-Power n-dimensional Gram–Schmidt Orthogonalization Architecture Design Methodology

Gram–Schmidt orthogonalization is a popular fundamental technique of linear algebra, having wide-spread applications in state-of-the art and next-generation signal processing and communication technologies including Blind Source Separation, Independent Component Analysis, MIMO technology, Orthogonal Frequency Division Multiplexing, and QR Decomposition. On the other hand, Coordinate Rotation Digital Computer (CORDIC) is a technique being extensively used for the efficient implementation of complex arithmetic operations in various signal processing and communication modules. For all the aforementioned applications including FastICA and QR decomposition, CORDIC is being used widely for all the modules except GS where still costly multipliers, dividers, square root, and addition operations are being used. It motivated us to investigate the design for GS using CORDIC resulting in low-power and low-complex architecture of the entire design. In this paper, we propose a CORDIC-based low-complexity, low-power architecture design methodology for the n-dimensional GS algorithm where a single CORDIC unit can be re-used for implementation of several processing and communication modules on-chip. The proposed architecture precludes the use of additional arithmetic units to perform costly operations by recursive use of CORDIC, and thus significantly reduces its hardware complexity. The proposed architecture reduces the power consumption by 74–86 $$\%$$ and the area by 12–40 $$\%$$ for 3D to 6D GS, respectively, over the conventional approach.