Novel approach for a monolithically integrated GaN cascode with minimized conduction and switching losses

In the power switching market, GaN-on-Si technology is competing at low to medium blocking voltages (200–900 V). The challenge to obtain a sufficiently high threshold voltage $(V_{\mathrm{th}})$ [1] at reasonably low conduction and switching loss ( $R_{\mathrm{ds},\mathrm{on}}$ and $Q_{\mathrm{gd}}$ ) limits current solutions to enhancement-mode (e-mode) p-GaN gated transistors (“gate inj ection transistor”, GIT) or depletion-mode (d-mode) [metal-insulator-semiconduc-tor] heterostructure field effect transistors ([MIS]-HFETs) in cascode configuration with a low-cost low-voltage (LV) Si e-mode MOSFET. While the latter has apparent disadvantages such as increased packaging cost, undesired “ringing” effects by external wiring inductance and an operation temperature that is limited by the Si device, the former device concept typically shows a trade-offbetween $V_{\mathrm{th}}$ and $R_{\mathrm{ds},\mathrm{on}}$ , i.e. the higher the targeted $V_{\mathrm{th}}$ , the higher is $R_{\mathrm{ds},\mathrm{on}}$ . Okita et al. have circumvented this trade-off by implementing a gate recess and p-GaN overgrowth [2]. However, the regrowth interface is subjected to the high-volt-age (HV) drain side, i.e. it can give rise to reliability issues. To overcome this, a novel monolithically integrated cascode is proposed in which a HV GaN d-mode (MIS-)HFET is controlled by a LV p-GaN gated e-mode device (Fig. 1a, b). This concept addresses several major challenges: 1. It enables high $V_{\mathrm{th}}$ without sacrificing $R_{\mathrm{ds},\mathrm{on}}$ ; 2. $C_{\mathrm{gd}}$ is effectively reduced during switch-off (miller effect leading to reduced switching losses [3]); 3. The reliability is enhanced with respect to the regrown p-GaN gated transistor and 4. Cost is low due to monolithic integration and standard CMOS-compatible building blocks.