Fast encoding of quasi-cyclic low-density parity-check codes in IEEE 802.15.3c

A high-speed encoder is proposed for quasi-cyclic low-density parity-check codes. By merging some sub-matrices of a parity-check matrix H in an approximately lower triangular form, a compact encoding process is obtained, reducing pipeline stages from six to three. Moreover, well-designed circuits are used to implement back-substitution and sparse-matrix–vector multiplication. The low-density parity-check (672, 336) code in IEEE 802.15.3c shows that the proposed encoder is easy to implement, runs fast, and requires no memory.