System level deterministic and random jitter measurement and extraction for multi-gigahertz memory buses

The data rate for today's computer systems now reaches several gigabits per second. For example, Rambus' XDR/spl trade/ memory system supports data rates from 2.4 Gbps to 8.0 Gbps. As in data communication systems, such as Gigabit Ethernet and fibre channel, measuring jitter and understanding the sources of jitter become a critical part of the design process of optimizing system performance. We present a measurement and extraction methodology for obtaining system level jitter in terms of deterministic and random jitter. A bit error rate (BER) model is created to estimate system margin at very low BER, which is too time consuming to obtain directly through measurement. Finally, the accuracy and validity of the proposed extraction methodology is quantified and verified.